Chip-specific system clock manager configuration.
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Defines |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
#define | CONFIG_SYSCLK_CPU_DIV 0 |
#define | CONFIG_SYSCLK_PBA_DIV 0 |
#define | CONFIG_SYSCLK_PBB_DIV 0 |
#define | CONFIG_SYSCLK_PBC_DIV 0 |
#define | CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 |
#define | CONFIG_USBCLK_DIV 1 |
#define | CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
#define | CONFIG_PLL0_MUL (64000000UL / BOARD_OSC0_HZ) |
#define | CONFIG_PLL0_DIV 1 |
#define | CONFIG_PLL1_SOURCE PLL_SRC_OSC0 |
#define | CONFIG_PLL1_MUL (48000000UL / BOARD_OSC0_HZ) |
#define | CONFIG_PLL1_DIV 1 |
Detailed Description
Chip-specific system clock manager configuration.
Copyright (C) 2011 Atmel Corporation. All rights reserved.